Testability access of the high speed test features in the Alpha 21264 microprocessor

Author

Bhavsar, Dilip K. ; Akeson, David R. ; Gowan, Michael K. ; Jackson, Daniel B.

Author_Institution

Alpha Technol. Group, Compaq Comput. Corp., Shrewsbury, MA, USA

fYear

1998

fDate

18-23 Oct 1998

Firstpage

487

Lastpage

495

Abstract

A novel on-chip testability access architecture provides comprehensive tester-driven access to the Alpha 21264 microprocessor´s testability features during manufacturing. It also allows simple automatic chip-initiated access that leverages the same features during normal chip operation. The architecture uses the IEEE Std 1149.1 to access all test features by creatively solving a number of problems in accessing the chip´s at-speed testability features from an asynchronous test port and slow tester

Keywords

automatic testing; boundary scan testing; built-in self test; design for testability; integrated circuit testing; microprocessor chips; Alpha 21264 microprocessor; IEEE 1149.1; asynchronous test port; at-speed testability; automatic chip-initiated access; boundary scan register; central controller; high speed test features; on-chip testability access architecture; self-test logic; slow tester; testability features during manufacture; tester-driven access; Automatic testing; CMOS technology; Computer aided manufacturing; Computer architecture; Costs; Design for testability; Integrated circuit testing; Logic arrays; Microprocessors; Pins;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1998. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-5093-6

Type

conf

DOI

10.1109/TEST.1998.743190

Filename

743190