A 8bit two stage time-to-digital converter using 16x cascaded time difference amplifier in 0.18um CMOS

We have designed a 8 bit two stage time-to-digital converter(TDC) using a time difference amplifier in 0.18 um CMOS process. The time resolution is 1.89 ps, and DNL of 0.9 and INL of 1.0 are achieved in simulation. To amplify the time residue of the first stage, the 16 x cascaded time difference amplifier(TDA) using differential logic delay cells is employed. By using differential logic cells for the delay chain instead of CMOS logic cells, the 16 x cascaded TDA realizes stable time difference gain(TD gain) and fine time resolution. The TDA have been fabricated in 0.18 um CMOS process. Measurement results show that our TDA achieves 4.4% TD gain offset at 30 ps input range, the standard deviation and the maximum error of the difference between the ideal amplified value and measured value is 13.0ps and 30.0 ps respectively. The maximum error corresponds to 0.99 LSB. Linearity of the two stage TDC depends on the specifications of a TDA greatly. The linearity of the proposed TDC improved by using the 16 x cascaded TDA and using only one TDA in the two stage TDC instead of using a lot of TDAs.