A scalable architecture for VLSI test

Author

Chang, Ed ; Cheung, David ; Huston, Robert ; Seaton, Jim ; Smith, Gary

Author_Institution

Credence Syst. Corp., Fremont, CA, USA

fYear

1998

fDate

18-23 Oct 1998

Firstpage

500

Lastpage

506

Abstract

The higher bandwidth of new embedded core components is increased by using two methods. The event frequency is increased by reducing the cycle time for I/O transactions. Where the laws of physics cause raw speed increases to be impractical, the bus width increases to handle a greater volume of data per unit time. This paper describes a test system architecture designed to meet the challenges of testing at higher data rates and efficient packaging for testing devices with large pin counts

Keywords

CMOS digital integrated circuits; VLSI; automatic test equipment; automatic test pattern generation; integrated circuit packaging; integrated circuit testing; thermal management (packaging); timing; I/O transactions; VLSI test; calibration; cycle time reduction; efficient packaging; embedded core components; event frequency; higher data rate testing; large pin count device testing; pattern memory; scalable CMOS; scalable architecture; test system architecture; thermal considerations; timing generation; vector sequence control; CMOS technology; Circuit testing; Electronic equipment testing; Electronics cooling; Frequency; Power generation; System testing; Test pattern generators; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1998. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-5093-6

Type

conf

DOI

10.1109/TEST.1998.743192

Filename

743192