Energy efficient design techniques for a digital signal processor

Power is often cited as a key design metric for IC designs. However, for many integrated solutions a better measure of design quality is the overall energy efficiency of the design as low power does not always imply high energy efficiency. Many design tradeoffs must be made to balance the often-conflicting goals of high performance, low power, small area and high efficiency. This paper will use the context of a DSP core design to examine a small subset of the full range of design techniques that can be leveraged to directly impact the overall energy efficiency of a design: clock gating and structured clock trees, pulse latches and other multi-bit design structures, 8T vs 6T SRAM arrays, low-voltage retention vs power collapse, aggressive process-variation-aware frequency/voltage scaling with support for both run-fast-and-sleep and just-in-time execution modes, integrated power management solutions.