Title :
Multi-threshold design methodology of stacked Si-nanowire FETs
Author :
Yi-Bo Liao ; Meng-Hsueh Chiang
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
A multi-threshold design methodology of stacked silicon nanowire MOSFETs is proposed. A flexible doping scheme is demonstrated for high-performance and low-operating power designs integrated together on a same substrate. With additional channel length adjustment, low standby power is further achieved.
Keywords :
field effect transistors; nanowires; semiconductor doping; silicon; Si; channel length adjustment; flexible doping scheme; low-operating power design; multithreshold design methodology; stacked silicon-nanowire FET; standby power; substrate; Design methodology; Doping; Logic gates; MOSFET; Silicon; System-on-chip; Wires;
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE
Conference_Location :
Millbrae, CA
DOI :
10.1109/S3S.2014.7028206
