Title :
Analog building block design in 14nm FinFET using inversion coefficient
Author :
Wang, A. ; Dhawan, V. ; Shi, C.-J.R.
Author_Institution :
Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA
Abstract :
This paper presents the characterization of inversion coefficient and technology current for 14nm FinFET. Analog performance parameters, their variability and controlability, including transconductance efficiency, intrinsic gain, gain-bandwidth product, flicker noise and current mismatching, are then characterized in terms of inversion coefficient. These characterized relations are used for sizing and dynamically compensating a set of analog building blocks including differential pairs, current mirrors, PTAT current generator, and re-generative structures. Post-layout simulation results using IBM´s 14nm SOI FinFET process are presented.
Keywords :
MOSFET; circuit layout; silicon-on-insulator; IBM SOI FinFET process; PTAT current generator; analog building block design; analog performance parameters; controlability; current mirrors; current mismatching; differential pairs; flicker noise; gain-bandwidth product; intrinsic gain; inversion coefficient; post-layout simulation; regenerative structures; size 14 nm; transconductance efficiency; variability; Delays; FinFETs; Generators; Integrated circuits; Performance evaluation; Temperature sensors;
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE
Conference_Location :
Millbrae, CA
DOI :
10.1109/S3S.2014.7028207
