Design and optimization of PWL circuits used in fuzzy logic hardware

This work is concerned with the design automation of analog circuits realizing piecewise linear functions (PWL) that may be used for fuzzy logic circuit design. There are several sources of systematic or random errors in the design of such functions. Various combinations of CMOS current mirror circuits are used to implement PWL functions. In order to simplify the optimization of implementation, PWL circuits are divided into smaller circuits which are assumed to be current mirrors in this work. This work presents a computer aided tool for calculation of optimized W and L values of current mirror transistors for various values of reference current within a specified error to find the best transistor parameters for possible minimum power dissipation. Results are tested on several applications to verify that the outputs of the computer aided system presented in this work match simulation results.