Title :
BIST circuit design for backplane interconnect test
Author :
Chang, Jong-Kwon
Author_Institution :
Dept. of Comput. Inf., Ulsan Univ., South Korea
Abstract :
Backplane is a well-known method for inter-board connections. These boards are usually plugged into the backplane of the communication systems and are used to exchange signal with each other via backplane interconnects. Faults can be incidentally introduced whenever a board is removed or replaced or added. Thus, the backplane interconnect testing is a very important process to verify the operation of the communication system. In this paper, a BIST (built-in self test) technique is adopted to minimize the cost of test equipment and to detect faults automatically. This BIST circuit was implemented using the N+1 algorithm to detect multiple faults and the IEEE Std. 1149.1 Boundary Scan Architecture methodology to inject test vectors
Keywords :
automatic testing; boundary scan testing; built-in self test; digital circuits; fault location; fault simulation; logic testing; printed circuit testing; BIST circuit design; IEEE 1149.1; backplane interconnect test; boundary scan architecture methodology; built-in self test technique; communication system; inter-board connections; multiple faults detection; test vectors injection; Automatic testing; Backplanes; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Electrical fault detection; Fault detection; Integrated circuit interconnections; System testing;
Conference_Titel :
Science and Technology, 1999. KORUS '99. Proceedings. The Third Russian-Korean International Symposium on
Conference_Location :
Novosibirsk
Print_ISBN :
0-7803-5729-9
DOI :
10.1109/KORUS.1999.876258
