On the validation of embedded systems through functional ATPG

Increasing size and complexity of digital designs has made essential to address critical verification issues at the early stages of design cycle. Therefore, automated verification tools are necessary at higher levels of abstraction, but they are still in a prototyping phase. In this context, a valuable solution for the functional validation is represented by dynamic verification which exploits simulation-based techniques to stimulate the whole design under verification (DUV). To perform dynamic verification it is necessary to generate test sequences to be simulated on the DUV. This paper describes a functional test pattern generator which exploits two different paradigms: high-level decision diagrams (HLDDs) and extended finite state machines (EFSMs). HLDDs and EFSMs are deterministically explored by using propagation, justification, learning and backjumping. The integration of such strategies allows the ATPG to more efficiently analyze the state space of the design under verification and to generate very effective test sequences.