Title :
Analytical modeling of parasitics in monolithically integrated 3D inverters
Author :
Lacord, J. ; Batude, P. ; Ghibaudo, G. ; Boeuf, F.
Author_Institution :
STMicroelectron., Crolles, France
fDate :
May 30 2012-June 1 2012
Abstract :
In this paper, we estimate using an analytical model the parasitic capacitances of 3D inverters based on 3D sequential integration. Total capacitance and delay are evaluated for two different contact schemes (plug and bar contact) and compared with a 2D reference.
Keywords :
capacitance; invertors; monolithic integrated circuits; semiconductor device models; 2D reference; 3D sequential integration; analytical modeling; contact schemes; monolithically integrated 3D inverters; parasitic capacitances; parasitics; plug and bar contact; Capacitance; Inverters; Layout; Logic gates; Plugs; Propagation delay; Transistors; 3D integration; FDSOI; delay; inverter; parasitic capacitance;
Conference_Titel :
IC Design & Technology (ICICDT), 2012 IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4673-0146-6
Electronic_ISBN :
pending
DOI :
10.1109/ICICDT.2012.6232856
