Title :
Near-0.1V ultra-low voltage operation of SOTB 1M logic gates
Author :
Ogasahara, Y. ; Hioki, M. ; Nakagawa, T. ; Sekigawa, T. ; Tsutsumi, T. ; Koike, H.
Author_Institution :
Nanoelectron. Res. Inst., AIST, Tsukuba, Japan
Abstract :
This paper demonstrates the near-0.1V minimum operation voltage of SOTB process for one million logic gates on silicon. In a circuit simulation, the lowest energy/cycle is estimated to be obtained at near 0.1V when near- or sub-60mV/dec. SS transistors are introduced, and lowering minimum operation voltage of logic circuit will be more important from the viewpoint of obtaining high energy efficiency. The variability is the main obstacle of low voltage operation, and lowering operation voltage to near 0.1V is difficult. Comparison of measurement results between 65nm SOTB and bulk processes indicate that the low-variability SOTB process notably lowers the minimum operation voltage to near 0.1V where high energy efficiency is obtained with near- or sub-60mV/dec. SS transistors in simulation.
Keywords :
logic circuits; logic gates; silicon; silicon-on-insulator; SOTB 1M logic gate; SS transistor; bulk process; energy efficiency; high energy efficiency; logic circuit voltage; silicon; silicon on thin buried oxide; size 65 nm; ultralow voltage operation; CMOS integrated circuits; Logic gates; MOS devices; Out of order; Semiconductor device measurement; Silicon; Substrates;
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE
Conference_Location :
Millbrae, CA
DOI :
10.1109/S3S.2014.7028217