DocumentCode
2525574
Title
Design and performance considerations for sub-0.1 /spl mu/m double-gate SOI MOSFET´S
Author
Hon-Sum Wong ; Frank, D.J. ; Yuan Taur ; Stork, J.M.C.
Author_Institution
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
1994
fDate
11-14 Dec. 1994
Firstpage
747
Lastpage
750
Abstract
We present a simulation-based analysis of the device design and circuit performance trade-offs between short channel immunity and parasitic device capacitances of sub-0.1 /spl mu/m double-gate SOI MOSFET´s. We demonstrate that perfect alignment of the bottom gate to the top gate is not necessary to achieve adequate short channel immunity but is required to maintain short gate delays. Double-gate MOSFET device design guidelines are provided.<>
Keywords
MOSFET; circuit analysis computing; delays; silicon-on-insulator; 0.1 micron; gate delays; parasitic device capacitances; performance; short channel immunity; sub-0.1 /spl mu/m double-gate SOI MOSFET; Analytical models; Circuit optimization; Circuit simulation; Degradation; Delay; Guidelines; MOSFET circuits; Monte Carlo methods; Parasitic capacitance; Performance analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International
Conference_Location
San Francisco, CA, USA
ISSN
0163-1918
Print_ISBN
0-7803-2111-1
Type
conf
DOI
10.1109/IEDM.1994.383315
Filename
383315
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