Author :
Subbanna, S. ; Ganin, E. ; Crabbe, E. ; Comfort, J. ; Wu, S. ; Agnello, P. ; Martin, B. ; McCord, M. ; Ng, H. ; Newman, T. ; McFarland, P. ; Sun, J. ; Snare, J. ; Acovic, A. ; Ray, A. ; Gehres, R. ; Schulz, R. ; Greco, S. ; Beyer, E. ; Liebmann, L. ; Dell
Author_Institution :
IBM Corp., Hopewell Junction, NY, USA
Abstract :
An integrated 0.35 /spl mu/m CMOS technology with 0.15 /spl mu/m effective channel length (L/sub EFF/) is demonstrated in a 200 mm line. X-ray lithography is used for the critical gate level, along with conventional deep-UV and mid-UV lithography for other levels. Shallow Trench Isolation (STI) is used to achieve 0.35 /spl mu/m design rules. The NFET and PFET devices are designed for operation with a scaled power supply of 1.8 V. This technology provides 50% performance improvement relative to a 2.5 V, 0.5 /spl mu/m design rule, 0.25 /spl mu/m L/sub EFF/ high-performance CMOS technology.<>
Keywords :
CMOS integrated circuits; X-ray lithography; integrated circuit technology; isolation technology; photolithography; 0.15 /spl mu/m channel-length; 0.15 mum; 0.35 mum; 1.8 V; 200 mm; 200 mm process integration; CMOS technology; NFET devices; PFET devices; X-ray lithography; critical gate level; deep-UV lithography; delay supply voltage behaviour; mid-UV lithography; optical lithography; scaled power supply; shallow trench isolation; CMOS process; CMOS technology; Fabrication; Isolation technology; Logic devices; Optimized production technology; Resists; Sun; X-ray imaging; X-ray lithography;
