Mixed-single well 8T SRAM bitcell for wide voltage range in 28nm FDSOI

Enabling high speed SRAM operation at low voltage is typically limited by variability and low device drivability. Most of the reported low-voltage SRAM bitcells show significant area penalty and low performances. This paper proposes a Mixed-Single Well (MSW) 8T SRAM bitcell, which takes advantage of wide back bias voltage range capability of ultra-thin body and box (UTBB) FD-SOI technology The bitcell is evaluated in 28nm using the read-after-write (RAW) dynamic metric which overcomes the limitations of standard readability (RA) and writeability (WA) approaches. It is demonstrated that body biasing tuning enables operation of the proposed bitcell at approx. 5.6s at 0.4V with over 100MHz.