Title :
A highly practical modified LOCOS isolation technology for the 256 Mbit DRAM
Author :
Ahn, D.H. ; Ahn, S.J. ; Griffin, P.B. ; Hwang, M.W. ; Lee, W.S. ; Ahn, S.T. ; Hwang, C.G. ; Lee, M.Y.
Author_Institution :
Samsung Electron. Co. Ltd., Kyungki, South Korea
Abstract :
We have developed a modified LOCOS isolation technology for the 256 Mbit DRAM. This novel Poly-Si Spacer LOCOS (PSL) isolation has been applied to build a 16 Mbit density DRAM with 256 Mbit (0.3 /spl mu/m) design rules. With the PSL isolation process, low bird´s beak encroachment, good vertical profile, clear definition of the active and field boundaries, high punchthrough voltage, and low leakage current have been achieved by simple fabrication processes.<>
Keywords :
DRAM chips; MOS memory circuits; integrated circuit technology; isolation technology; oxidation; 0.3 mum; 256 Mbit; DRAM; LOCOS isolation technology; bird´s beak encroachment; cross-sectional SEM; design rules; field oxidation; gate oxide reliability; low leakage current; polysilicon spacer LOCOS; punchthrough voltage; vertical profile; Buffer layers; Ear; Etching; Isolation technology; Low voltage; Mice; Oxidation; Random access memory; Research and development; Silicon;
Conference_Titel :
Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2111-1
DOI :
10.1109/IEDM.1994.383321
