Title :
Robust PEALD SiN spacer for gate first high-k metal gate integration
Author :
Triyoso, D.H. ; Jaschke, V. ; Shu, J. ; Mutas, S. ; Hempel, K. ; Schaeffer, J.K. ; Lenski, M.
Author_Institution :
GLOBALFOUNDRIES, Dresden, Germany
fDate :
May 30 2012-June 1 2012
Abstract :
As we packed more and more transistors into one chip and as the size of transistor continues to shrink, the need for conformal sidewall protection layer becomes critical. In this work improved device properties is demonstrated using PEALD SiN spacer compared to the conventional PECVD SiN spacer.
Keywords :
CMOS integrated circuits; silicon compounds; CMOS; PEALD SiN spacer; SiN; conformal sidewall protection layer; device property improvement; gate first high-k metal gate integration; transistor; Atomic layer deposition; Films; Loading; Logic gates; Plasma temperature; Silicon compounds; ALD; SiN; high-k metal gate; iso-dense loading; spacer;
Conference_Titel :
IC Design & Technology (ICICDT), 2012 IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4673-0146-6
Electronic_ISBN :
pending
DOI :
10.1109/ICICDT.2012.6232870
