Unifying design data during verification: Implementing Logic-Driven Layout analysis and debug

At 65 nm and below, parametric yield loss has become the predominant yield-limiting factor, making the analysis and optimization of electrical performance crucial to market success. Until now, however, the full efficacy of electrical design for manufacturing (EDFM) tools has been limited by the separation of detailed physical layout information from both detailed knowledge of design intent and the logical circuits implemented by the layout. We introduce a Logic-Driven Layout Framework that provides EDFM tools with unified access to all types of design data (physical, logical, electrical) in a single environment, enabling circuit designers to quickly identify and debug potential parametric issues, and, without losing domain context, share their findings with designers working in different design domains (logic, layout, manufacturing, etc.).