DocumentCode :
252590
Title :
SEU Hardening: Incorporating an Extreme Low Power Bitcell Design (SHIELD)
Author :
Pescovsky, A. ; Chertkow, O. ; Atias, L. ; Fish, A.
Author_Institution :
VLSI Syst. Center, Ben-Gurion Univ. of the Negev, Beer-Sheva, Israel
fYear :
2014
fDate :
6-9 Oct. 2014
Firstpage :
1
Lastpage :
3
Abstract :
The pursuit of continuous scaling of electronic devices in the semiconductor industry has led to two unintended but significant outcomes: a rapid increase in susceptibility to radiation induced errors and an overall rise in power consumption. Operating under low voltage to reduce power only aggravates radiation related reliability issues. In this paper, a novel “SEU Hardening Incorporating Extreme Low Power Bitcell Design” (SHIELD) is proposed to attend these two major concerns simultaneously. The SHIELD bitcell tolerates upsets with charge deposits over 1 pC when operated at a scaled 700mV supply voltage utilizing a 65nm process. Simulations confirm its advantages in terms of leakage power, with more than twofold lower leakage currents than previous solutions.
Keywords :
integrated circuit reliability; leakage currents; low-power electronics; radiation hardening (electronics); scaling circuits; SEU hardening incorporating extreme low power bitcell design; SHIELD bitcell; electronic device scaling; leakage current; leakage power; power consumption; radiation induced error; reliability issue; semiconductor industry; single event upset; size 65 nm; voltage 700 mV; Inverters; Logic gates; Single event upsets; Standards; Transient analysis; Transistors; Turning;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE
Conference_Location :
Millbrae, CA
Type :
conf
DOI :
10.1109/S3S.2014.7028236
Filename :
7028236
Link To Document :
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