DocumentCode
2525922
Title
Design of an ultra-low power time interleaved SAR converter
Author
Erario, Fabrizio ; Agnes, Andrea ; Bonizzoni, Edoardo ; Maloberti, Franco
Author_Institution
Dept. of Electron., Univ. of Pavia, Pavia
fYear
2008
fDate
June 22 2008-April 25 2008
Firstpage
245
Lastpage
248
Abstract
An ultra low-power SAR ADC is presented. The circuit is the interleaved version of an already designed SAR converter with improved performance. This design uses 7 interleaved converters and achieves a conversion rate of 700 kS/s. The converter has been simulated by using a 0.18-mum CMOS technology showing a power consumption as low as 40 muW which allows obtaining a state-of-the-art FoM equal to 37 fJ/conv.-step. The architectural study together with converter simulation results are presented.
Keywords
CMOS integrated circuits; analogue-digital conversion; low-power electronics; ADC; CMOS technology; power 40 muW; size 0.18 mum; successive approximation register; ultra-low power time interleaved converter; Attenuation; CMOS technology; Capacitors; Circuit topology; Energy consumption; Pipelines; Sampling methods; Sensor systems; Signal resolution; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Research in Microelectronics and Electronics, 2008. PRIME 2008. Ph.D.
Conference_Location
Istanbul
Print_ISBN
978-1-4244-1983-8
Electronic_ISBN
978-1-4244-1984-5
Type
conf
DOI
10.1109/RME.2008.4595771
Filename
4595771
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