A symmetric Vss cross-under bitcell technology for 64 Mb SRAMs

Author

Pfiester, J.R. ; Hayden, S.D. ; Thompson, M. ; Miller, F. ; Lin, H.-J. ; Blackwell, M.J. ; Mocala, K. ; Ku, Y.-C. ; Subramanian, C.K. ; Waldo, W. ; Ajuria, S. ; James, B.M. ; Martino, B.

Author_Institution

Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA

fYear

1994

fDate

11-14 Dec. 1994

Firstpage

623

Lastpage

626

Abstract

A 0.25 /spl mu/m CMOS technology designed for a new symmetric Vss Cross-Under (XUnder) bitcell has been developed for a 64 Mb SRAM. The new symmetric bitcell is based on a simple geometry of orthogonal active and gate poly features which minimizes the height/width aspect ratio of the bitcell, resulting in a wider column decoder pitch. A new inverted spacer TFT has been adopted as the load element in the bitcell. Bitcell features fabricated using X-ray lithography demonstrate that a simple NCL isolation approach can be used to define 0.625 /spl mu/m active pitch features without evidence of oxide punchthrough thus alleviating the need for more aggressive approaches such as shallow trench isolation.<>

Keywords

CMOS memory circuits; SRAM chips; X-ray lithography; isolation technology; 0.25 micron; 64 Mbit; CMOS technology; LOCOS-based isolation; NCL isolation; SRAM; X-ray lithography; column decoder pitch; cross-under bitcell technology; inverted spacer TFT; static RAM; symmetric Vss technology; CMOS technology; Decoding; Etching; Laboratories; Oxidation; Random access memory; Research and development; Thin film transistors; Variable structure systems; X-ray lithography;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-2111-1

Type

conf

DOI

10.1109/IEDM.1994.383333

Filename

383333