Title :
BGA packaging using insulated wire for die area reduction
Author :
Kumar, S. ; Garg, V. ; Verma, C. ; Bhooshan, R. ; Poh Zi-Song ; Tan, L.C.
Author_Institution :
Freescale Semicond. India, Noida, India
Abstract :
In conventional wire bonded packages, design rules require that individual bond wires not touch each other. Also, handling of bonded units may cause wire disturbance leading to wire short. Insulated wire bonding techniques eliminate this requirement by coating a non conductive layer over the bond wires as shown in Fig.1 and thus, electrical isolation is maintained even after wires physically touch each other [1-2]. The focus of this paper is to leverage the insulated wire-bonding technology for die design implementation efficiency in terms of improving electrical parameters and die size reduction. Two specific implementation are discussed in this paper. One is to implement off-chip decoupling capacitor and use it to replace on-die capacitors required for signal integrity and save precious silicon area. Second implementation is about realizing mesh type power grid to improve the IR drop and simultaneously get rid of multiple Power/Ground pads and thus, save silicon area.
Keywords :
ball grid arrays; insulated wires; lead bonding; silicon; BGA packaging; IR drop; ball grid array packaging; die area reduction; die size reduction; electrical isolation; ground pad; insulated wire bonding technology; mesh type power grid; nonconductive layer; off-chip decoupling capacitor; on-die capacitor; signal integrity; silicon area; wire bonded package; wire disturbance; Bonding; Capacitance; Capacitors; Packaging; Power grids; Silicon; Wires;
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2014 IEEE 16th
Conference_Location :
Singapore
DOI :
10.1109/EPTC.2014.7028271