Self-aligned tungsten strapped source/drain and gate technology realizing the lowest sheet resistance for sub-quarter micron CMOS

Author

Sekine, M. ; Inoue, K. ; Ito, H. ; Honma, I. ; Miyamoto, H. ; Yoshida, K. ; Watanabe, H. ; Mikagi, K. ; Yamada, Y. ; Kikkawa, T.

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Kanagawa, Japan

fYear

1994

fDate

11-14 Dec. 1994

Firstpage

493

Lastpage

496

Abstract

This paper describes a self-aligned tungsten strapped source/drain and gate with the lowest sheet resistance for subquarter micron CMOS. Vapor HF selective etching was applied for grooved gate structure fabrication. Selective tungsten chemical vapor deposition (W-CVD) with high pressure nucleation step was applied to fabricate tungsten strapped CMOS with recessed tungsten on poly-Si gate. The sheet resistances of 0.125 /spl mu/m wide gate and 0.25 /spl mu/m wide diffusion layer were 0.9 /spl Omega/sq. and 1.8 /spl Omega/sq. for NMOS and PMOS, respectively. This is the lowest among reported values. By using this technology, 0.22 /spl mu/m tungsten strapped CMOS was successfully fabricated.<>

Keywords

CMOS integrated circuits; chemical vapour deposition; etching; integrated circuit metallisation; tungsten; 0.22 micron; IC fabrication; W; W strapped source/drain; W-Si; chemical vapor deposition; grooved gate structure fabrication; high pressure nucleation step; poly-Si gate; recessed W; selective W CVD; self-aligned gate; self-aligned source/drain; sheet resistance; subquarter micron CMOS; vapor HF selective etching; CMOS process; CMOS technology; Contamination; Etching; Fabrication; Hafnium; Ion implantation; MOS devices; Silicon; Tungsten;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-2111-1

Type

conf

DOI

10.1109/IEDM.1994.383361

Filename

383361