Title :
A 0.05 /spl mu/m-CMOS with ultra shallow source/drain junctions fabricated by 5 keV ion implantation and rapid thermal annealing
Author :
Hori, A. ; Nakaoka, H. ; Umimoto, H. ; Yamashita, K. ; Takase, M. ; Shimizu, N. ; Mizuno, B. ; Odanaka, S.
Author_Institution :
Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan
Abstract :
A 0.05 /spl mu/m-PMOSFET has been fabricated for the first time, together with a 0.05 /spl mu/m-NMOSFET. For this process, ultra shallow source/drain junctions were developed on the basis of 5 keV ion implantation technology and rapid thermal annealing. The short channel effect was suppressed and Gm max reaches 460 mS/mm for NMOS and 380 mS/mm for PMOS. The delay time per stage of unloaded CMOS inverter is 13.1 psec at the supply voltage of 1.5 V.<>
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit technology; ion implantation; rapid thermal annealing; 0.05 micron; 1.5 V; 380 mS/mm; 460 mS/mm; 5 keV; CMOS process; NMOSFET; PMOSFET; RTA; ion implantation; rapid thermal annealing; short channel effect suppression; ultra shallow source/drain junctions; CMOS technology; Capacitance; Electrodes; Etching; Ion implantation; MOS devices; Rapid thermal annealing; Rapid thermal processing; Very large scale integration; Voltage;
Conference_Titel :
Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2111-1
DOI :
10.1109/IEDM.1994.383363
