Through silicon via (TSV) scallop smoothening technique

Author

Goon Heng Wong ; King Jien Chui ; Guan Kian Lau ; Woon Leng Loh ; Li HongYu

Author_Institution

Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore

fYear

2014

fDate

3-5 Dec. 2014

Firstpage

676

Lastpage

678

Abstract

To achieve high performance in a small form factor and to overcome Moore Law´s by still achieving more transistors on microchips are through 2.5D and 3D chips stacking [1]. Through Si via (TSV) is the key to 2.5 D and 3D technology and is gaining more and more interest from many giant chipmakers [2]. Various defects may form during silicon etch in TSV due to the etching mechanism [3].

Keywords

etching; three-dimensional integrated circuits; 3D chip stacking; 3D technology; Moore law; Si; TSV scallop smoothening technique; etching mechanism; microchip; through silicon via technology; Cleaning; Dielectrics; Etching; Microelectronics; Silicon; Three-dimensional displays; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging Technology Conference (EPTC), 2014 IEEE 16th

Conference_Location

Singapore

Type

conf

DOI

10.1109/EPTC.2014.7028274

Filename

7028274

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=252661