DocumentCode
2526709
Title
Degradation of I/O devices due to ESD-induced dislocations
Author
Hashimoto, C. ; Okuyama, K. ; Kubota, K. ; Ishizuka, H.
Author_Institution
Hitachi ULSI Eng. Corp., Tokyo, Japan
fYear
1994
fDate
11-14 Dec. 1994
Firstpage
459
Lastpage
462
Abstract
Degradation in leakage current characteristics of I/O circuits due to ESD events has been studied. TEM observations revealed the generation of crystalline defects in the silicon substrate such as dislocations induced by ESD stress which increased the reverse leakage current level of the p-n junctions in the I/O circuits. We found that current crowding occurs in the silicon surface region during an ESD event resulting in defect generation. We also show that optimal impurity profiles for protection devices can avoid such current crowding and hence the leakage current degradation.<>
Keywords
MOS integrated circuits; dislocations; doping profiles; electrostatic discharge; failure analysis; integrated circuit reliability; leakage currents; protection; silicon; transmission electron microscopy; CMOS IC; ESD stress; ESD-induced dislocations; I/O device degradation; MOS IC; Si; Si substrate; Si surface region; TEM observations; crystalline defects; current crowding; defect generation; leakage current characteristics; optimal impurity profiles; p-n junctions; protection devices; reverse leakage current level; Circuits; Crystallization; Degradation; Electrostatic discharge; Impurities; Leakage current; P-n junctions; Proximity effect; Silicon; Stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International
Conference_Location
San Francisco, CA, USA
ISSN
0163-1918
Print_ISBN
0-7803-2111-1
Type
conf
DOI
10.1109/IEDM.1994.383369
Filename
383369
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