Title :
Detecting resistive shorts for CMOS domino circuits
Author :
Chang, Jonathan T Y ; McCluskey, Edward J.
Author_Institution :
Center for Reliable Comput., Stanford Univ., CA, USA
Abstract :
We investigate defects in CMOS domino gates and derive the test conditions for them. Very-Low-Voltage Testing can improve the defect coverage, which we define as the maximum detectable resistance, of intra-gate and inter-gate resistive shorts. We also propose a new keeper design for CMOS domino circuits. The new keeper design has low performance impact and is best for small CMOS domino gates. Keepers can eliminate the floating nodes in CMOS domino logic gates
Keywords :
CMOS logic circuits; fault diagnosis; integrated circuit testing; logic gates; logic testing; CMOS domino circuits; defect coverage; domino gates; floating nodes; inter-gate resistive shorts; intra-gate resistive shorts; keeper design; maximum detectable resistance; very-low-voltage testing; CMOS logic circuits; Circuit faults; Circuit noise; Circuit testing; Clocks; Delay; Logic gates; Low voltage; Temperature; Threshold voltage;
Conference_Titel :
Test Conference, 1998. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5093-6
DOI :
10.1109/TEST.1998.743280
