DocumentCode
252702
Title
Room temperature and zero pressure high quality oxide direct bonding for 3D self-aligned assembly
Author
Dubey, Vikas ; Van Huylenbroeck, Stefaan ; Tutunjyan, Nina ; Slabbekoorn, John ; De Wolf, Ingrid ; Rebibis, Kenneth June ; Miller, Alice ; Celis, Jean Pierre ; Croes, Kristof ; Beyne, Eric
Author_Institution
IMEC, Leuven, Belgium
fYear
2014
fDate
3-5 Dec. 2014
Firstpage
579
Lastpage
582
Abstract
To keep up with the pace of decreasing transistor channel length, the demand for smaller pitch size is pushing 3D IC research into new approaches for stacking. As the pitch size decreases, the thickness of interconnection also decreases. During stacking, a small misalignment may lead to poor interconnection or even connection failure. This has led 3D IC research to pursue higher alignment accuracy during stacking. One such stacking approach that is being considered is 3D self-alignment. To facilitate highly accurate alignment it is also important to have good quality immediate bonding that can further reduce chances of misalignment during handling. In this work, we demonstrate a very high quality bonding between two similar dies with oxide capping layer, as well as different cleaning approach and the bonding test.
Keywords
bonding processes; cleaning; self-assembly; stacking; three-dimensional integrated circuits; transistors; 3D IC research; 3D self-aligned assembly; alignment accuracy; cleaning approach; connection failure; good quality immediate bonding test; handling; interconnection thickness; oxide capping layer; room temperature quality oxide direct bonding; smaller pitch size; stacking approach; transistor channel length; zero pressure high quality oxide direct bonding; Accuracy; Bonding; Cleaning; Stacking; Surface contamination; Surface treatment; Three-dimensional displays;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference (EPTC), 2014 IEEE 16th
Conference_Location
Singapore
Type
conf
DOI
10.1109/EPTC.2014.7028296
Filename
7028296
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