A non-enumerative path delay fault simulator for sequential circuits

We extend the path status graph (PSG) method of delay fault simulation to sequential circuits. By devising a layered PSG and restricting the number of time-frames over which a fault must be detected, we preserve the non-enumerative nature of the simulation algorithm. The program is capable of simulating a wide variety of circuits (synchronous, asynchronous, multiple-clock and tri-state logic.) Both rated and variable clock modes, as well as robust, non-robust or functional sensitization detection options, are available. The simulation can be stopped and restarted through a check pointing facility. The program can target any given list of paths. This path list can also be generated by the program based on user-selectable criteria (all paths, longest paths, paths between certain I/O pairs, etc.) User reports include a histogram of path coverage versus path length. Detected and undetected path data remain implicit in the PSG and can be retrieved through post-processing commands. Due to its non-enumerative stature, the program can process most production level digital logic circuits