Chip scale package with low cost substrate evaluation and characterization

In recent years, low cost solution was demanded to develop for Chip scale package series package to achieve the same performance or better than original. Regarding this requirement, the low cost substrate (coreless substrate) was developed to replace traditional substrate to achieve this target easily such as Molded Interconnection System BGA (MISBGA), Embedded Trace Substrate (ETS) and Single Layer Substrate (SLP) to effectively shrink package thickness, provide equivalent or more I/O interconnections and low cost solution. This paper will aim to investigate CSP package characteristics with MISBGA, ETS and SLP substrate by using Finite Element Method (FEM) to discover the strong and weak point in those coreless substrates. According to previous experience, the warpage performance of coreless substrates would become more sensitive than traditional substrate since no rigid core material supporting package. Therefore, the higher accuracy of predictive warpage from simulation would become more important in FEM model. Based on that, this study will input TMA&DMA material property measuring in house instead of traditional data sheet material property and also consider the structure tolerance and material property tolerance into the FEM model to show maximum, mean and minimum predictive warpage which method is more similar with real moiré measurement data to check the warpage to meet criteria or not. According to lots simulation work, it is successful to apply low cost solution of coreless substrate into novel CSP series and also can achieve shrinking package thickness, equivalent or more I/O interconnections and better thermal capability advantages from new warpage simulation methodology and thermal prediction.