DocumentCode
2527208
Title
Defining ATPG rules checking in STIL
Author
Wohl, Peter ; Waicukauski, John
Author_Institution
Synopsis Inc., Williston, VT, USA
fYear
1998
fDate
18-23 Oct 1998
Firstpage
971
Lastpage
979
Abstract
Developed for pattern interchange from test-generation output to tester input, the standard test interface language (STIL) was recently shown to support general test-generation input constructs. This paper shows how scan-test rules-checking can be driven by a single STIL input file. All rules-checking information can be read back in to iteratively refine rules checking
Keywords
automatic test pattern generation; automatic testing; boundary scan testing; high level languages; integrated circuit testing; iterative methods; ATPG rules checking; STIL input file; iterative refinement; pattern interchange; scan-test rules-checking; standard test interface language; test-generation input constructs; test-generation output; tester input; Automatic test pattern generation; Automatic testing; Hardware design languages; Integrated circuit testing; Libraries; Performance evaluation; Standards development; Test equipment; Test pattern generators; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1998. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-5093-6
Type
conf
DOI
10.1109/TEST.1998.743293
Filename
743293
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