• DocumentCode
    2527251
  • Title

    On/off-current ratios of transfer-free bilayer graphene FETs as a function of temperature

  • Author

    Wessely, P.J. ; Wessely, F. ; Birinci, E. ; Schwalke, U. ; Riedinger, B.

  • Author_Institution
    Inst. for Semicond. Technol. & Nanoelectron., Tech. Univ. Darmstadt, Darmstadt, Germany
  • fYear
    2012
  • fDate
    16-18 May 2012
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    In this paper we report on a novel method to fabricate graphene transistors directly on oxidized silicon wafers without the need to transfer graphene. By means of catalytic chemical vapor deposition (CCVD) the in-situ grown bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate. These BiLGFETs possess unipolar p-type device characteristics with an extremely high on/off-current ratio between 1×106 and 1×107 at room temperature [1, 2], exceeding previously reported values by several orders of magnitude. Furthermore, when increasing the ambient temperature to 200°C, the on/off-current ratio only degrades by one order of magnitude for BiLGFETs. Besides the excellent device characteristics, the complete CCVD fabrication process is silicon CMOS compatible. This will allow a simple and low-cost integration of graphene devices for nanoelectronic applications in a hybrid silicon CMOS environment.
  • Keywords
    CMOS integrated circuits; chemical vapour deposition; field effect transistors; graphene; nanoelectronics; silicon; BiLGFET; CCVD fabrication process; catalytic chemical vapor deposition; graphene transistor fabrication; hybrid silicon CMOS environment; in-situ grown bilayer graphene transistors; nanoelectronic application; on/off-current ratio; oxidized silicon substrate; oxidized silicon wafer; silicon CMOS compatibility; temperature 200 C; transfer-free bilayer graphene FET; unipolar p-type device characteristics; CMOS integrated circuits; Fabrication; Films; Silicon; Substrates; Temperature; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2012 7th International Conference on
  • Conference_Location
    Gammarth
  • Print_ISBN
    978-1-4673-1926-3
  • Type

    conf

  • DOI
    10.1109/DTIS.2012.6232950
  • Filename
    6232950