Title :
A goal tree based high-level test planning system for DSP real number models
Author :
Lin, Morris ; Armstrong, J.R. ; Gray, F.G.
Author_Institution :
VLSI Technol. Center, Hewlett-Packard Co., Fort Collins, CO, USA
Abstract :
This paper presents a high-level test planning system for validating DSP real number models. It uses a goal tree structure as a framework of test planning and documenting. The goal tree based test plans are linked to the test bench generator, which creates test benches for simulation. The simulation results are checked and fed back to the test plans and new test benches are created accordingly. A GUI-based integrated software system has been developed for test planning and test automation based on this methodology. To illustrate this methodology, this paper uses the Synthetic Aperture Radar system as a case study. Finally, completeness and effectiveness of the generated test set are evaluated using structural approaches. Results of test set compaction are also presented
Keywords :
application specific integrated circuits; digital signal processing chips; graphical user interfaces; hardware description languages; integrated circuit testing; logic testing; DSP real number models; GUI-based integrated software system; IC testing; VHDL; goal tree; high-level test planning system; structural approaches; synthetic aperture radar system; test automation; test bench generator; test set compaction; Application specific integrated circuits; Automatic testing; Circuit synthesis; Circuit testing; Digital signal processing; Hardware design languages; Integrated circuit synthesis; Process design; Software testing; System testing;
Conference_Titel :
Test Conference, 1998. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5093-6
DOI :
10.1109/TEST.1998.743297