Detection of bridging faults in logic resources of configurable FPGAs using IDDQ

This paper presents an I_DDQ-based test strategy for detecting bridging faults in the logic resources of reprogrammable field programmable gate arrays (FPGAs). The approach utilizes the programmability of the configurable logic blocks (CLBs) to achieve 100% coverage of I_DDQ-testable bridging faults. Since reconfiguration programming time can dominate total test time, even with slow I_DDQ vectors, we use a bottom-up test generation approach to minimize the number of programming phases first, and then to minimize the number of test vectors. 100% coverage for I_DDQ-testable bridging faults is achieved in 5 programming phases and 16 I_DDQ vectors in the Xilinx XC4000 FPGA family. The RAM modes are tested in a further phase, using 48 test vectors and 38 I_DDQ measurements