DocumentCode
2527401
Title
Deterministic BIST with multiple scan chains
Author
Kiefer, Gundolf ; Wunderlich, Hans-Joachim
Author_Institution
Comput. Archit. Lab., Stuttgart Univ., Germany
fYear
1998
fDate
18-23 Oct 1998
Firstpage
1057
Lastpage
1064
Abstract
A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simultaneously and guarantees complete fault coverage. The new scheme may require less chip area than a classical LFSR-based approach while better or even complete fault coverage is obtained at the same time
Keywords
automatic test pattern generation; boundary scan testing; built-in self test; fault simulation; flip-flops; logic testing; m-sequences; minimisation of switching nets; shift registers; XOR gates; circuits with multiple scan paths; complete fault coverage; deterministic BIST scheme; flip-flops; logic minimization; multiple scan chains; parallel scan; pattern generator synthesis; pseudo-random patterns; reflipping; sequence-generating logic; Automatic testing; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Computer architecture; Hardware; Registers; Signal generators; Signal synthesis;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1998. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-5093-6
Type
conf
DOI
10.1109/TEST.1998.743304
Filename
743304
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