A diagnostic test generation procedure for synchronous sequential circuits based on test elimination

We propose a procedure for generating test sequences for diagnosis of synchronous sequential circuits based on stuck-at faults. The test generation procedure avoids the conventional fault-oriented test generation by observing that a sequence to distinguish two faults can be obtained from a sequence that detects both of the faults (such as a test sequence for fault detection) by changing the sequence so as to “undetect” one of the faults. To achieve this goal, the proposed procedure eliminates parts of a test sequence for fault detection so as to render some of the faults undetected. The faults that are detected by the resulting sequence are distinguished from the faults left undetected by the sequence based on pass/fail information. A pass/fail dictionary suitable for diagnosis with the resulting test sequences is also proposed. Alternatively, a conventional dictionary can be used, and the proposed procedure can be used to change the time units or outputs where faults are detected, in order to distinguish them. We present experimental results to demonstrate the levels of resolution that can be obtained by the proposed procedure with the proposed pass/fail dictionary, and the number of sequences required for this purpose