Microprocessor technology trends

During the next 5 years, with supply voltages below 2.5 volts, CMOS processes will provide worst case 32 bit adder delays below 1.0 ns with minimum Leff below 0.25 microns. CMOS processor frequencies will increase above 350 MHz for highly pipelined servers, and above 200 MHz for low power notebooks. With the increase in power, circuit design methods for low power notebooks will diverge from highly pipelined servers. Die size will not increase due to interconnect delay limitations and fabrication costs. This will reduce the rate of increase in transistor count on one die. Circuit techniques will be applied to achieve higher functionality per transistor and reduce power, delay, and area. BiNMOS will not maintain sufficient advantage over CMOS to be useful at voltages below 2.5 volts.<>