A mesochronous outfit for Network-on-Chip´s interconnects retiming

Current VLSI systems-on-Chips (SoCs) integrate billions of transistors and are clocked with multi-gigahertz clock frequencies. As the geometrical dimensions of both devices and wires in theses systems become smaller, the internal communication performance between the SoC´s blocks is heavily affected by the on-chip interconnect wire delays. In this paper, we propose a high efficient mesochronous outfit for network on chip (NoC) interconnects retiming. The proposed solution resolves the problem of clock skew and signal delays by using a delay locked loop (DLL) and a strobe signal to gauge the phase difference between two clock domains in a SoC. The asynchronism problem in the system is avoided by a data retiming accomplished by delaying signals with the mean of controllable delay buffers. The outfit foster alleviates the system´s design complexity and results in a significant gain in their performances. The proposed device was implemented in 250 nm process technology and simulated for the worst case conditions using Tanner tool. Under a 3.3 V power supply and synched with a 800 MHz clock, the synchronizer consumes about 33.4 mW per bitline at room temperature.