DocumentCode :
2527794
Title :
An input multiplexed current mode transmitter for on-chip global interconnects
Author :
Anusha, G. ; Venkateshwarlu, P. ; Murugeshwari, P. ; Bhaskar, Manoj ; Venkataramani, B.
Author_Institution :
Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Trichy
fYear :
2008
fDate :
19-21 Nov. 2008
Firstpage :
1
Lastpage :
5
Abstract :
In the literature, both current mode and voltage mode multiplexers are proposed for transmitters used to drive global interconnects. Current mode multiplexers operate at higher speeds at the cost of increase in power dissipation. In this paper, a novel technique is proposed to increase the operating speed of the current mode multiplexer by reducing the impedance at the output of the multiplexer. This is achieved by connecting a diode connected transistor as the load. The proposed transmitter is implemented using 180 nm technology and studied through simulation with Synopsys HSPICE assuming an interconnect of length 7 mm. It is found through simulation, that the interconnect driven by this transmitter has a lower delay by a factor of two compared to that obtained using repeater insertion technique. The proposed transmitter is also compared with that using output multiplexing scheme. It is found that the operating bandwidth of the proposed transmitter is two and half times more than that of output multiplexed transmitter. Both rise time and power dissipation are lower by a factor of two for the proposed transmitter compared to the output multiplexed transmitter with four inputs.
Keywords :
SPICE; VLSI; current-mode circuits; integrated circuit interconnections; multiplexing equipment; repeaters; HSPICE; VLSI technology; diode connected transistor; multiplexed current mode transmitter; on-chip global interconnect; power dissipation; repeater insertion technique; voltage mode multiplexer; Costs; Delay; Diodes; Impedance; Joining processes; Multiplexing; Power dissipation; Repeaters; Transmitters; Voltage; Current mode multiplexer; Input multiplexed transmitter architecture; large bandwidth; less delay; less power; output multiplexed transmitter architecture;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
TENCON 2008 - 2008 IEEE Region 10 Conference
Conference_Location :
Hyderabad
Print_ISBN :
978-1-4244-2408-5
Electronic_ISBN :
978-1-4244-2409-2
Type :
conf
DOI :
10.1109/TENCON.2008.4766583
Filename :
4766583
Link To Document :
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