DocumentCode
2527834
Title
IC diagnosis: preventing wars and war stories
Author
Saxena, Jayashree
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
1998
fDate
18-23 Oct 1998
Firstpage
1138
Abstract
Failure analysis is one of the most challenging tasks in IC manufacturing today. Every failed die clamours for individual attention and the task of finding the defect which is the root cause of the problem can take hours to a few days. Automation aids in a very limited way in this area and this inevitably leads to wars. So how do we prevent wars in IC diagnosis? Some suggestions are given for improving design for diagnosis, fault modelling and diagnosis algorithms, and defect excitation
Keywords
automatic test pattern generation; design for testability; fault simulation; integrated circuit testing; logic testing; DFT techniques; IDDQ testable; IC diagnosis; IC manufacturing; automated logic diagnosis; defect excitation; delay faults; design for diagnosis; failure analysis; fault diagnosis algorithms; fault modelling algorithms; pattern content; root cause analysis; stuck at faults; test generation; Circuit faults; Delay; Failure analysis; Fault detection; Fault diagnosis; Instruments; Manufacturing automation; Observability; Sequential circuits; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1998. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-5093-6
Type
conf
DOI
10.1109/TEST.1998.743329
Filename
743329
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