Abstract :
A system chip is defined as a complete system implemented on a single IC such that no peripheral chips are required. Thus, a system chip typically contains embedded core logic, embedded memory and analog components. A key enabling component of system chips is the re-use of existing design components sometimes called intellectual property cores or virtual components. Design re-use is narrowing the system chip design productivity gap but test and verification are now becoming the bottleneck. The key issues in testing core based system chips are how to optimally provide test access and test isolation to allow test methods and test vectors to be re-used for an embedded core, while ensuring that area, performance, test time and at-speed test requirements are met. While we are still in the early stages of developing a core test methodology that is widely accepted, two promising test re-use techniques are emerging: the test bus and test rail methods. Both approaches address the test bandwidth problem by allowing expandible test data access
Keywords :
application specific integrated circuits; automatic testing; boundary scan testing; built-in self test; design for testability; electronic design automation; integrated circuit testing; BIST; analog components; at-speed test requirements; boundary scan; core based system chips; design productivity gap; design re-use; electronic design automation tools; embedded core logic; embedded memory; expandible test data access; functional test; intellectual property cores; plug and play; single IC; system chip test; system on chip; test access; test and verification; test bandwidth problem; test bus; test isolation; test planning; test rail; virtual components; Automatic testing; Built-in self-test; Chip scale packaging; Electronic design automation and methodology; Logic testing; Rails; Silicon; System testing; System-on-a-chip; Virtual colonoscopy;
