BIST vs. ATE: need a different vehicle?

Author

Sunter, Stephen

Author_Institution

LogicVision, San Jose, CA, USA

fYear

1998

fDate

18-23 Oct 1998

Firstpage

1148

Abstract

Ask ASIC designers whether they plan to use BIST, and the answer will depend on whether the designer has seen the `swamp´ of test complexity for deep submicron ICs. With gate counts >500 K and internal clock rates >200 MHz, test costs can equal silicon costs unless embedded test facilities are used. For these ICs, which are quickly becoming mainstream, which functions are best tested with BIST? An attempt is made to answer this question, and it is concluded that, compared to external ATE, BIST can be more effective for testing multiple embedded memories, high speed random logic, and some mixed-signal functions. It is recommended that designers and test engineers should anticipate the approaching swamp of test complexity and decreasing test yields

Keywords

application specific integrated circuits; automatic testing; built-in self test; design for testability; integrated circuit testing; ASIC design; ATE; BIST; decreasing test yields; deep submicron IC; embedded test facilities; high speed random logic; mixed-signal functions; multiple embedded memories; system on chip; test complexity; test costs; virtual test; Automatic test pattern generation; Built-in self-test; Circuit testing; Clocks; Costs; Frequency; Integrated circuit testing; Logic design; Pins; Vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1998. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-5093-6

Type

conf

DOI

10.1109/TEST.1998.743348

Filename

743348