Title :
TCAD strategy for predictive VLSI memory development
Author :
Masuda, H. ; Sato, H. ; Tsuneno, K. ; Aoyama, I. ; Nakamura, T. ; Kunitomo, H. ; Kajigaya, K.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
This paper describes a methodology of TCAD application in VLSI design and development. Simulation-based predictive circuit model parameter generation for chip design purposes is one of the key topics in TCAD. A process and device database has been constructed, which is used in newly developed TCAD global calibrations in conjunction with a statistical process-recipe design at sub-half micron level. One month of TCAD was required to generate an optimized sub-half micron process and devices and channel-length dependent MOS model parameters. It was verified that the generated MOS circuit model agrees well with experiments within the predicted process fluctuation limit due to the proposed global TCAD calibration technique.<>
Keywords :
VLSI; circuit CAD; integrated circuit design; integrated memory circuits; simulation; 0.5 micron; MOS circuit model; TCAD strategy; VLSI design; channel-length dependent MOS model parameters; chip design; global calibrations; optimized subhalf micron process; predictive VLSI memory development; predictive circuit model parameter generation; simulation-based parameter generation; statistical process-recipe design; subhalf micron level; Calibration; Chip scale packaging; Circuit simulation; Circuit testing; Integrated circuit interconnections; Performance evaluation; Predictive models; Process design; Response surface methodology; Very large scale integration;
Conference_Titel :
Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2111-1
DOI :
10.1109/IEDM.1994.383442
