Title :
Chip package interaction induced ILD integrity issues in fine pitch flip chip packages
Author :
Gupta, V. ; O´Connor, S. ; Pilch, C.
Author_Institution :
Semicond. Packaging, Texas Instrum., Inc., Dallas, TX, USA
Abstract :
Thermal compression bonding is being widely used for fine pitch copper pillar assembly as it provides high die placement accuracy and bonding suitable for mass production. In the current work, chip package interaction induced ILD integrity failures under thermo-compression assembly induced stresses were investigated. A step by step EFA (Electrical Failure Analysis) plus PFA (Physical Failure Analysis) methodology was developed to isolate the failing location and confirm the fail mode. The key steps include initially dataloging the fails and running the data through ATPG (Automatic Test Pattern Generation) tools to localize the failing nets. The PFA was then focused on the ILD sections in the vicinity of the Cu pillar interconnect (as the pillar is the primary load transference link between the die and substrate). Specific fail modes were then identified using a combination of Scanning Optical Microscopy (SOM), Scanning Acoustic Microscopy (SAM), layer by layer de-processing and Focused Ion Beam (FIB) cross-sections. The paper summarizes the key findings, failure modes from the study - it was found that the assembly process could result in damage initiation in the ILD which results in functional failures during subsequent reliability testing. The scale of induced damage makes it nearly impossible to detect using either traditional eFA, PFA or a combination of the two. Additionally, key assembly and design parameters, to resolve the fails are also discussed.
Keywords :
automatic test pattern generation; failure analysis; flip-chip devices; focused ion beam technology; optical microscopy; tape automated bonding; ATPG tools; EFA; FIB sections; PFA; SOM; automatic test pattern generation tools; chip package interaction; electrical failure analysis; fine pitch copper pillar assembly; fine pitch flip chip packages; focused ion beam sections; high die placement accuracy; induced ILD integrity issues; mass production; physical failure analysis methodology; primary load transference link; scanning optical microscopy; thermal compression bonding; thermocompression assembly induced stresses; Assembly; Automatic test pattern generation; Bonding; Bonding forces; Dielectrics; Failure analysis; Stress;
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2014 IEEE 16th
Conference_Location :
Singapore
DOI :
10.1109/EPTC.2014.7028362