Title :
Multiplier reduction tree with logarithmic logic depth and regular connectivity
Author :
Eriksson, H. ; Larsson-Edefors, Per ; Sheeran, Mary ; Sjalander, M. ; Johansson, Dan ; Scholin, M.
Author_Institution :
Dept. of Comput. Sci. & Eng., Chalmers Univ. of Technol., Goteborg
Abstract :
A novel partial-product reduction circuit for use in integer multiplication is presented. The high-performance multiplier (HPM) reduction tree has the ease of layout of a simple carry-save reduction array, but is in fact a high-speed low-power Dadda-style tree having a worst-case delay which depends on the logarithm (O(log TV)) of the word length N
Keywords :
carry logic; logic design; multiplying circuits; trees (mathematics); HPM reduction tree; high-performance multiplier reduction tree; high-speed Dadda-style tree; integer multiplication; logarithmic logic depth; low-power Dadda-style tree; partial-product reduction circuit; regular connectivity; word length; worst-case delay; Adders; Buildings; Circuits; Computer science; Delay; Logic arrays; Logic design; Power generation; Time division multiplexing; Wire;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1692508
