Title :
Implementation of a high-speed low-power 32-bit adder in 70nm technology
Author :
Kashfi, Fatemeh ; Fakhraie, S. Mehdi
Author_Institution :
Sch. of ECE, Tehran Univ.
Abstract :
In this article, the performance and power dissipation of two differential logic circuits in deep sub-micron technologies are obtained and compared together, and the superior topology is introduced. Low voltage swing (LVS) technique which improves circuit performance and lowers power consumption is described in detail. We conclude this article with the design, simulation and optimization of a high speed low-power 32-bit adder using the LVS technique in 70nm technology. This circuit can operate at 10GHz clock frequency with power dissipation as low as 2.58 mW/GHz
Keywords :
adders; logic circuits; low-power electronics; network topology; 10 GHz; 32 bit; 70 nm; LVS; adder design; adder optimization; adder simulation; circuit performance; deep submicron technologies; differential logic circuits; high-speed low-power adder; low power consumption; low voltage swing; power dissipation; Adders; Circuit optimization; Circuit simulation; Circuit topology; Clocks; Design optimization; Energy consumption; Logic circuits; Low voltage; Power dissipation;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1692509
