Title :
0.15 /spl mu/m CMOS process for high performance and high reliability
Author :
Shimizu, S. ; Kuroi, T. ; Kobayashi, M. ; Yamaguchi, T. ; Fujino, T. ; Maeda, H. ; Tsutsumi, T. ; Hirose, Y. ; Kusunoki, S. ; Inuishi, H. ; Tsubouchi, N.
Author_Institution :
ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
We have developed a novel 0.15 /spl mu/m CMOS process for high performance and high reliability, consisting of mixing the CoSi/sub 2/-Si interface using Si/sup +/ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using these processes, the propagation delay time of 21 psec/stage was obtained for a 0.15 /spl mu/m CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.<>
Keywords :
CMOS integrated circuits; integrated circuit reliability; integrated circuit technology; ion implantation; nitrogen; silicon; 0.15 micron; 2 V; CMOS process; CoSi/sub 2/-Si; N implantation; Si/sup +/ implantation; gate-around mask; high performance; high reliability; hot-carrier degradation; junction capacitance reduction; oxide reliability; propagation delay time; ring oscillator; selective channel implantation; shallow junctions; CMOS process; Capacitance; Doping; Electrodes; Leakage current; Morphology; Nitrogen; Silicidation; Threshold voltage; Writing;
Conference_Titel :
Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2111-1
DOI :
10.1109/IEDM.1994.383465
