Energy efficient design for subthreshold supply voltage operation

Subthreshold design has become an important area in low-power design due to its ultra-low power consumption and high energy efficiency. This is very useful in mobile applications where battery life is crucial. For most current DVS processor designs, the voltage range is limited from full V_dd to approximately half V_dd at most. Subthreshold design enables wide-range dynamic voltage scaling (DVS) by allowing circuits to operate in subthreshold voltages. In this paper we give an overview of several issues in energy-efficient subthreshold design. First, from a theoretical point of view, we show that, for subthreshold supply-voltages, leakage energy becomes dominant, making "just in time completion" energy inefficient. We derive an analytical model for the minimum energy-optimal voltage and study its trends with technology scaling. Second, we evaluate different low-power approaches such as MTCMOS (multiple-threshold CMOS) and DVS and show that wide-range DVS provides the best energy efficiency. Finally, we study the impact of process variation on subthreshold operation and discuss which sources of process variation are dominant in this regime and how they can be addressed