Title :
Package characterization of UTAC´s Grid Array package (GQFN) and performance comparison over standard laminate packages
Author :
Teh, D.T.L. ; Tubillo, C.E. ; Kyaw Ko Lwin ; Gu Bin ; Dimaano, A.C.G.J. ; Sirinorakul, S. ; Suthiwongsunthorn, N.
Author_Institution :
United Test & Assembly Center Ltd., Singapore, Singapore
Abstract :
The increasing demand and requirements for package with smaller footprint, higher dense I/O counts and better performance at lower cost are one of the key challenges faced by semiconductor manufacturing companies. As one of the strategies for sustainable competitive advantages and to address the issue, UTAC introduced a new generation of leadframe package design called Grid Array QFN (GQFN), where base material is leadframe but allows traces to be routed through etching process, hence providing higher I/Os that to date have required a two or four layers of laminate base packages. GQFN also has much smaller package form factor with reduction of package size up to 60%, shorter wire length with lower parasitic values and the feasibility to include a die attach paddle whilst having array of solder balls simultaneously. GQFN technology allows flip chip, stacked die, multi-chip module, passive integration and to meet the demand in leadless lead-frame applications. As part of package characterization, this package is subjected to comprehensive package analysis study using simulation and experimental data. In order to demonstrate the advantages and benefits of the package, this study projects the performance of GQFN to laminates package as a benchmark. Analysis methodologies and results of thermal, electrical and mechanical performance study will be discussed in detailed. From the comparative analysis study conducted, the overall thermal and electrical performance of GQFN is better than laminate packages. The package also has good results to meet the test requirement according to the IPC/JEDEC standards showing that the mechanical performance of GQFN is comparable to laminate packages.
Keywords :
etching; integrated circuit packaging; multichip modules; GQFN technology; IPC-JEDEC standards; UTAC grid array package; comprehensive package analysis; dense I-O counts; die attach paddle; etching process; flip chip; grid array QFN; lead frame package design; leadless lead-frame applications; multichip module; passive integration; solder balls; stacked die; standard laminate packages; Conferences; Electronics packaging;
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2014 IEEE 16th
Conference_Location :
Singapore
DOI :
10.1109/EPTC.2014.7028389