New erase scheme for DINOR flash memory enhancing erase/write cycling endurance characteristics

Author

Tsuji, N. ; Ajika, N. ; Yuzuriha, K. ; Kunori, Y. ; Hatanaka, M. ; Miyoshi, H.

Author_Institution

ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan

fYear

1994

fDate

11-14 Dec. 1994

Firstpage

53

Lastpage

56

Abstract

New erase scheme for DINOR (Divided Bit Line NOR) flash memory is proposed and investigated, which utilizes substrate hot electron(SHE) injection instead of FN tunnel injection for erasure. Additional process or alteration of the cell structure is not needed to realize SHE erasure. The cell is formed in a triple well structure. The bottom n-well layer, which surrounds the p-well, is used as electron supply source in the SHE. By adopting SHE for erasure, the electric field required across the tunnel oxide was reduced to 1/4, compared with FN erasure. It needs less than 1 second for erasure, which is sufficient for DINOR operation. It is shown that V th window narrowing during erase/write cycling was significantly reduced by using SHE for erasure, as compared with using FN tunneling. The mechanism of enhanced erase/write cycling endurance is also examined.<>

Keywords

CMOS memory circuits; EPROM; hot carriers; 1 sec; DINOR flash memory; EEPROM; SHE erasure; V th window narrowing; divided bit line NOR type; electric field reduction; erase scheme; erase/write cycling endurance characteristics; substrate hot electron injection; triple well CMOS structure; tunnel oxide; CMOS process; Electron emission; Flash memory; Flash memory cells; Laboratories; Low voltage; Testing; Tunneling; Ultra large scale integration; Vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-2111-1

Type

conf

DOI

10.1109/IEDM.1994.383468

Filename

383468