• DocumentCode
    2528934
  • Title

    Functional analysis of circuits under timing variations

  • Author

    Dehbashi, Mehdi ; Fey, Görschwin ; Roy, Kaushik ; Raghunathan, Anand

  • Author_Institution
    Inst. of Comput. Sci., Univ. of Bremen, Bremen, Germany
  • fYear
    2012
  • fDate
    28-31 May 2012
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    Summary form only given. This work proposes an approach to model and evaluate the functional behavior of logic circuits under timing variations. In the approach, first we construct a Time Accurate Model (TAM) of the circuit to represent its timing behavior in a functional domain under a discrete time model. Then, timing variations are applied by using Variation Logic (VL).
  • Keywords
    logic circuits; timing circuits; TAM; discrete time model; functional analysis; time accurate model; timing variation logic circuit; Approximation methods; Clocks; Computational modeling; Design automation; Integrated circuit modeling; Logic gates; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium (ETS), 2012 17th IEEE European
  • Conference_Location
    Annecy
  • Print_ISBN
    978-1-4673-0696-6
  • Electronic_ISBN
    978-1-4673-0695-9
  • Type

    conf

  • DOI
    10.1109/ETS.2012.6233031
  • Filename
    6233031
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2528934